A 2.5 Gb/s, low power clock and data recovery circuit

被引：0
|
作者：
Du, Qingjin
Zhuang, Jingcheng
Kwasniewski, Tad
机构：
来源：
2007 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-3 | 2007年
关键词：
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
This paper presents an all-digital clock and data recovery circuit with the data bit rate of 2 to 5Gb/s. With the eye-tracking technique instead of the traditional data edge tracking method, the jitter tolerance is increased by keeping the sampling clock away from the jitter distribution region confirmed by Matlab simulation. A bang-bang PD with a phase distance of 1/4 UI is chosen, and a jitter tolerance of 0.75UI is achieved. A CMOS circuit was implemented in CMOS90nm technology with low complexity. The circuit consumes a power of 9mW at 2.5 Gbps at a 1.2 v supply.
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收藏
页码：526 / 529
页数：4
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