Copper Pillar Voids in a Flip Chip Package During High Temperature Application

被引：1
|
作者：
Wang, Miao [1 ]
Mavinkurve, Amar [2 ]
Roucou, Romuald [2 ]
Afripin, Amirul [3 ]
Uehling, Trent [1 ]
Foong, Cs [1 ]
Lakhera, Nishant [1 ]
机构：
[1] NXP Semicond, Austin, TX 78736 USA
[2] NXP Semicond, Nijmegen, Netherlands
[3] NXP Semicond, Petaling Jaya, Malaysia
来源：
2023 IEEE 73RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC | 2023年
关键词：
Solder void; solder joint; Flip Chip; DoE; modeling; SOLDER;
D O I：
10.1109/ECTC51909.2023.00147
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents the results of a set of designed experiments for the purpose of evaluating the dependencies of solder voids on different factors related to package design after acceleration under high temperature stresses. The solder joints were studied with the help of SEM and image processing software to measure the void area. It was observed that the total solder height and the substrate stiffness play important roles in solder void formation. Besides, other factors such as shape of the solders and underfill material properties were also relevant. A mechanical model was built to focus on the impact of volume shrinkage by Cu-Sn intermetallic compounds formation. Simulations were carried out for the purpose of verifying the proposed voiding mechanisms for the different factors qualitatively. This paper provides more insightful understanding to help guiding package design for voiding control and predicting proper accelerating thermal aging conditions for reliability assessment.
引用
收藏
页码：852 / 857
页数：6
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