Copper Pillar Bumped Sapphire Flip Chip on Lead-frame Package Development

被引：0
|
作者：
John, Zhiyuan Yang [1 ]
机构：
[1] Peregrine Semicond, San Diego, CA 92121 USA
来源：
2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2012年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In the development of copper pillar bumped sapphire flip chip on lead-frame package (FCOLF), the die was found very vulnerable in assembly process. In the package reliability test the bump connection opened on the die side where the failure was initiated with cracks on die re-passivation layer. In order to find the root cause, comprehensive investigations have been carried out on wafer bumping quality check, bump and package structure finite element analysis as well as assembly process test etc. The results of the analysis & experiment as well as the process solution for volume production are presented in this paper.
引用
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页码：457 / 464
页数：8
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