Temperature and Humidity Stress Failure on Copper Pillar (CuP) Flip Chip Package Device

The combined benefits of reduced package footprint, higher input/output capability, better power and ground distribution and reduced signal inductance has made the flip chip package technology a primary packaging solution for portable consumer electronics as well as commercial/industrial applications. The technology qualification step ensures the highest quality and reliability performance on devices shipped out to the customers. In this paper, we present the detection of extrinsic failure modes due to wafer saw workmanship issues resulting to lateral crack from the edge towards the active layer of the device as well as damage to the die seal under severe temperature, humidity and bias conditions during reliability testing. Electrical fault isolation and copper pillar flip chip package-designed physical failure analysis are also presented. Assembly process controls addressing the root cause are also outlined to eliminate the contribution of the manufacturing process to the intrinsic failure mechanisms that the reliability testing aims to exacerbate.