Detection and Fault Isolation of Elevated Resistive Paths in Copper Pillar (CuP) Flip Chip Package Device

The demand for higher input/output (I/O) capability, smaller package footprint, low cost, combined with good electrical properties and better electromigration performance has made the copper pillar (CuP) bump an excellent first-level interconnect in flip chip devices built in the recent years. The ability to successfully qualify a new package technology, for this case, CuP flip chip, is dependent on a robust package design, an optimal and stable assembly process, a comprehensive stress plan, and of equal importance, is the development of an electrical test methodology that can detect issues exacerbated by the stress, as well as, the availability of fault isolation methods to rootcause these failures. In this paper, we present the detection of both intrinsic and extrinsic CuP bump interconnect reliability issues exacerbated by temperature cycling through the boundary scan test. The CuP flip chip package-designed electrical and physical failure analyses (FA) used to rootcause the failures were presented. Assembly process improvements to address the root cause of the extrinsic failure modes, as well as interconnect design improvements, to eliminate the contribution of the manufacturing process/package design to the intrinsic failure mechanisms reliability testing aims to expose, were also discussed.