Effective Package FA procedures on Flip Chip Ball Grid Array (FCBGA) Package with Copper Pillar (CuP) bumps

被引：0

作者：

Bailon-Somintac, Michelle ^{[1
]}

Oco, Jennyvie ^{[1
]}

Paderes, Dennis ^{[1
]}

Nguyen, Toan ^{[2
]}

机构：

[1] Lattice Semicond PH Corp, 11-F Aeon Ctr,Northbridgeway, Muntinlupa, Philippines

[2] Lattice Semicond Corp, 5555 NE Moore Ct, Hillsboro, OR 97124 USA

来源：

2018 25TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA) | 2018年

关键词：

flip chip; Copper Pillar bumps; bump on pad; decapsulation; package failure analysis;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Overcoming challenges not only in the design and assembly manufacturing but also in the physical failure analysis of flip-chip BGA packages with Cu pillar (CuP) bumps is of outmost importance especially with the increasing utilization of this package type in various market segments including the rapidly evolving consumer and mobile market. In this paper, we present innovative and effective methodologies for physical failure analysis on flip chip ball grid array (FCBGA) package with Copper (Cu) pillar bumps. The procedure that will be discussed does not require new failure analysis equipment but rather a reuse and extension of existing equipment used on standard wire-bond packages. Case studies to demonstrate the usefulness of the methodologies will also be presented.

引用

页数：5

共 50 条

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