Copper Pillar Voids in a Flip Chip Package During High Temperature Application

This paper presents the results of a set of designed experiments for the purpose of evaluating the dependencies of solder voids on different factors related to package design after acceleration under high temperature stresses. The solder joints were studied with the help of SEM and image processing software to measure the void area. It was observed that the total solder height and the substrate stiffness play important roles in solder void formation. Besides, other factors such as shape of the solders and underfill material properties were also relevant. A mechanical model was built to focus on the impact of volume shrinkage by Cu-Sn intermetallic compounds formation. Simulations were carried out for the purpose of verifying the proposed voiding mechanisms for the different factors qualitatively. This paper provides more insightful understanding to help guiding package design for voiding control and predicting proper accelerating thermal aging conditions for reliability assessment.