Design of Low Power and Robust Asynchronous SRAM Generated Using AMC Involving SAHB Circuit with QDI Logic

In the contemporary era, achieving enhanced performance in application-specific integrated circuit (ASIC) designs necessitates the development of memory circuits with minimal latency and reduced power consumption. Open-source memory compilers that support asynchronous chip design and offer flexibility for technology portability play a crucial role in facilitating academic research. This paper introduces an asynchronous memory compiler (AMC) framework designed to generate asynchronous static random access memory (SRAM) with a parameterizable layout independent of technology constraints. The framework adopts a pipelined memory bank architecture, incorporating split and merge control circuitry. Utilizing multi-threshold CMOS (MTCMOS) techniques, the memory compiler produces a low power 6 T SRAM circuit, effectively reducing leakage current. The inclusion of a low power sense amplifier half buffer (SAHB) circuit features a robust design employing quasi delay-insensitive (QDI) logic, contributing to minimizing power dissipation and enhancing tolerance to process, voltage, and temperature (PVT) variations. The outcomes of this work demonstrate an average power dissipation reduction of 64%, coupled with a 5% reduction in area requirements, achieved through the implementation of SAHB in 0.5 µm technology. © The Institution of Engineers (India) 2024.