TESTABLE PLA DESIGN WITH MINIMAL OVERHEADS

被引：2

作者：

YANG, TC ^{[1
]}

CHIOU, CW ^{[1
]}

机构：

[1] NATL CHENG KUNG UNIV,INST ELECT & COMP ENGN,TAINAN,TAIWAN

来源：

INTEGRATION-THE VLSI JOURNAL | 1990年 / 10卷 / 01期

关键词：

design-for-testing; programmable logic array (PLA); testable design; VLSI testing;

D O I：

10.1016/S0167-9260(05)80032-X

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new technique which uses extra inputs to make PLA testable is presented. A revised rule to modify the product lines of the PLA is given. No extra product lines are added as the revised rule is applied to the PLA. Fewer extra inputs than other existing comparable techniques are required to make the modified PLA testable, and therefore fewer extra overheads are added. The faults detected by this method include any number of stuck-at faults, any number of missing device faults, and any number of extra device faults. Even the redundant extra and missing device faults in the AND plane and OR plane are covered by this method. © 1990 Elsevier Science Publishers B.V.

引用

页码：9 / 18

页数：10

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