共 50 条
- [1] Testable Design of Repeaterless Low Swing On-Chip Interconnect PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, : 563 - 566
- [2] An On-Chip Delay Measurement Using Adjacency Testable Scan Design 2015 7th International Conference on Information Technology and Electrical Engineering (ICITEE), 2015, : 508 - 513
- [7] UNITARY OPTIMIZATION DESIGN FOR THE LARGE AIRCRAFT STRUCTURE. Ku Ti Li Hsueh Hsueh Pao/Acta Mechanica Solida Sinica, 1986, (03): : 216 - 228
- [8] ACCURATE HOMOLOGOUS DESIGN AND OPTIMIZATION OF AN ANTENNA STRUCTURE. Ku Ti Li Hsueh Hsueh Pao/Acta Mechanica Solida Sinica, 1986, (03): : 189 - 197
- [9] Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores Journal of Electronic Testing, 2002, 18 : 487 - 501
- [10] Design for consecutive testability of system-on-a-chip with built-in self testable cores JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2002, 18 (4-5): : 487 - 501