TESTABLE PLA DESIGN WITH MINIMAL OVERHEADS

被引：2
|
作者：
YANG, TC [1 ]
CHIOU, CW [1 ]
机构：
[1] NATL CHENG KUNG UNIV,INST ELECT & COMP ENGN,TAINAN,TAIWAN
来源：
INTEGRATION-THE VLSI JOURNAL | 1990年 / 10卷 / 01期
关键词：
design-for-testing; programmable logic array (PLA); testable design; VLSI testing;
D O I：
10.1016/S0167-9260(05)80032-X
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new technique which uses extra inputs to make PLA testable is presented. A revised rule to modify the product lines of the PLA is given. No extra product lines are added as the revised rule is applied to the PLA. Fewer extra inputs than other existing comparable techniques are required to make the modified PLA testable, and therefore fewer extra overheads are added. The faults detected by this method include any number of stuck-at faults, any number of missing device faults, and any number of extra device faults. Even the redundant extra and missing device faults in the AND plane and OR plane are covered by this method. © 1990 Elsevier Science Publishers B.V.
引用
收藏
页码：9 / 18
页数：10
相关论文
共 50 条
  • [31] Delay testable logical circuit design
    Matrosova, A. Yu
    Nikolaeva, E. A.
    Rumyantseva, E. V.
    RUSSIAN PHYSICS JOURNAL, 2013, 55 (11) : 1370 - 1372
  • [32] Whose job is it to design testable ASICs?
    Rincon, AM
    Lackey, D
    COMPUTER DESIGN, 1996, 35 (12): : 83 - &
  • [33] Design of testable random bit generators
    Bucci, M
    Luzzi, R
    CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2005, PROCEEDINGS, 2005, 3659 : 147 - 156
  • [34] A NEW APPROACH TO THE DESIGN OF TESTABLE PLAS
    REDDY, SM
    HA, DS
    IEEE TRANSACTIONS ON COMPUTERS, 1987, 36 (02) : 201 - 211
  • [35] Design of online testable fast divider
    Nagamani, A. N.
    Supreetha, N. J.
    2013 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN COMMUNICATION, CONTROL, SIGNAL PROCESSING AND COMPUTING APPLICATIONS (IEEE-C2SPCA-2013), 2013,
  • [36] Testable axion-like particles in the minimal linear σ model
    Alonso-Gonzalez, J.
    Merlo, L.
    Pobbe, F.
    Rigolin, S.
    Sumensari, O.
    NUCLEAR PHYSICS B, 2020, 950
  • [37] Design of Testable Reversible Sequential Circuits
    Thapliyal, Himanshu
    Ranganathan, Nagarajan
    Kotiyal, Saurabh
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (07) : 1201 - 1209
  • [38] MINIMAL COVERING PROBLEM AND PLA MINIMIZATION
    YOUNG, MH
    MUROGA, S
    INTERNATIONAL JOURNAL OF COMPUTER & INFORMATION SCIENCES, 1985, 14 (06): : 337 - 364
  • [39] ON THE DESIGN OF A HIGHLY TESTABLE CELL LIBRARY
    SARAIVA, M
    SANTOS, MB
    CASIMIRO, AP
    TEIXEIRA, IM
    TEIXEIRA, JP
    MICROPROCESSING AND MICROPROGRAMMING, 1992, 35 (1-5): : 383 - 390
  • [40] DEPENDABLE DYNAMIC PARTIAL RECONFIGURATION WITH MINIMAL AREA & TIME OVERHEADS ON XILINX FPGAS
    Di Carlo, Stefano
    Gambardella, Giulio
    Indaco, Marco
    Prinetto, Paolo
    Rolfo, Daniele
    Trotta, Pascal
    2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS, 2013,
12345