DESIGN OF EASILY TESTABLE ITERATIVE SYSTEMS

被引:0
|
作者
RUBIO, A [1 ]
机构
[1] ETSEIB UPC,DEPT ENGN ELECTR,E-08028 BARCELONA,SPAIN
来源
MICROPROCESSING AND MICROPROGRAMMING | 1987年 / 20卷 / 1-3期
关键词
D O I
10.1016/0165-6074(87)90132-3
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:141 / 146
页数:6
相关论文
共 50 条
  • [1] EASILY TESTABLE ITERATIVE SYSTEMS
    FRIEDMAN, AD
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1973, C 22 (12) : 1061 - 1064
  • [3] DESIGN OF EASILY TESTABLE BIT-SLICED SYSTEMS
    SRIDHAR, T
    HAYES, JP
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1981, 30 (11) : 842 - 854
  • [4] DESIGN OF EASILY TESTABLE BIT-SLICED SYSTEMS
    SRIDHAR, T
    HAYES, JP
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1981, 28 (11): : 1046 - 1058
  • [5] EASILY TESTABLE ITERATIVE LOGIC-ARRAYS
    WU, CW
    CAPPELLO, PR
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1990, 39 (05) : 640 - 652
  • [6] DESIGN OF EASILY TESTABLE LOGIC
    ROMANKEVICH, AM
    STUKACH, ND
    [J]. AUTOMATION AND REMOTE CONTROL, 1991, 52 (03) : 428 - 434
  • [7] DESIGN AND TESTING OF EASILY TESTABLE PLA
    MOTTALIB, MA
    DASGUPTA, P
    [J]. IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1991, 138 (05): : 357 - 360
  • [8] Design of a fast, easily testable ALU
    Blanton, RD
    Hayes, JP
    [J]. 14TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1996, : 9 - 16
  • [9] THE DESIGN OF EASILY TESTABLE VLSI ARRAY MULTIPLIERS
    SHEN, JP
    FERGUSON, FJ
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1984, 33 (06) : 554 - 560
  • [10] EASILY TESTABLE DESIGN OF LARGE DIGITAL CIRCUITS
    FUNATSU, S
    WAKATSUKI, N
    YAMADA, A
    [J]. NEC RESEARCH & DEVELOPMENT, 1979, (54): : 49 - 55