Analysis of Different SRAM Cell Topologies and Design of 10T SRAM Cell with Improved Read Speed

The aim of this paper is to analyze the read behaviour of the multiple SRAM cell structures using cadence tool at 45nm technology and to compare the cells for read operation while keeping the read and write access time and the supply voltage as low as possible. In particular, the leakage currents, leakage power and read behaviour of each SRAM cells are examined. A 10T SRAM cell implementation is proposed here that results in reduced leakage power and leakage current, at the same time with increased read stability in comparision with the conventional 6T SRAM cell as well as 7T, 8T and 9T SRAM cells. As a result, the 10T SRAM always consumes lowest leakage power and leakage current; improve read stability as compared to the 6T, 7T, 8T and 9T SRAM cells.