10T SRAM Design By Using Stack Transistor Technique

This proposed work covers the stack transistor technique by using 10-transistor (10T) static random access memory (SRAM) design. Which is used to reduce the leakage current and similarly power dissipation is reduced. The conventional 6T SRAM is prone to noise during read operation. Hence researchers proposed different topologies like 8T, 9T, and 10T. This will improve the stability but increases leakage noise. This work proposes novel design of 8T SRAM which is reducing leakage noise along with the power dissipation. For the last few years the reduction of leakage current as well as power dissipation in CMOS has been the researchers interest. The power dissipation and the leakage power consumption plays an important role in today's CMOS technology. As this proposed work used here stack transistor technology, it requires limited power and reduced the leakage current as a result the proposed work becomes more power efficient design. Novel design of 8T SRAM using stacked transistor technique which requires limited power and reduces leakage noise current and the design recovers as power efficient.