Design and Implementation of Low Power High Speed Robust 10T SRAM

The traditional SRAM cell enables high density and fast differential sensing but is subjected to semi-selective and read-risk problems. While a traditional eight-transistor SRAM cell solves the reading disruption issue, the performance of the reading bit-line (RBL) swing and ion / off ratio deteriorates, with raising the number of cells per column is still small. Low efficiency, data-dependent leakage, widefield, and high energy per connection have been influenced by previous strategies for solving these problems. Therefore, three SRAM bit cell iterations with only nMOS-based read ports are introduced in this article, aiming at considerably reducing data-dependent read-port leakage to allow 1k cells / RBL, increase read-performance and reduce the area and power of traditional and 10 T cell works. Throughout the simulations of a 128-kb SRAM, which is designed with a divided-word line-decoding design and a 32-bit word resolution, the proposed study is contrasted with other works. In addition to the significant improvements over standard cells, the read-reading efficiency of up to 100 mV, up to 19,8 percent energy saving per connection and up to 19,5 percent savings in the region were also observed compared with other 10 T cells, which improves the memory architecture and application range for designers in low-power sensors and battery-enabled applications.