Design of a high performance CNFET 10T SRAM cell at 5nm technology node

被引：2

作者：

Yang, Zihao ^{[1
,2
,3
]}

Yin, Minghui ^{[1
,2
,3
]}

You, Yunxia ^{[1
,2
,3
]}

Li, Zhiqiang ^{[1
,2
,3
]}

Liu, Xin ^{[2
]}

Zhang, Weihua ^{[1
,2
,3
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, EDA Ctr, Beijing 100029, Peoples R China

[2] Univ Chinese Acad Sci, Beijing 100049, Peoples R China

[3] Beijing Key Lab Three Dimens & Nanometer Integrate, Beijing 100029, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2023年 / 20卷 / 12期

关键词：

CNFET; SRAM; static power consumption; read static noise margin(RSNM); energy-delay-product(EDP); CARBON NANOTUBES;

D O I：

10.1587/elex.20.20230171

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This article proposes a CNFET 10T SRAM cell based on Stanford Virtual Source model at 5nm technology node, through optimization design and simulation analysis to select optimum gate widths of transistors to ensure best performance in terms of stability, speed and power consumption. We compare the proposed 10T CNFET SRAM with the optimized 6T CNFET SRAM in [9]. It was found that the timing and power characteristics of the proposed 10T SRAM cell is better than that of the 6T structure, the static power consumption is greatly reduced while the RSNM is improved by 93.5%, read and write EDP are improved by 68.5% and 96%, respectively.

引用

页数：6

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