Gate-Level Circuit Reliability Analysis: A Survey

被引:8
|
作者
Xiao, Ran [1 ]
Chen, Chunhong [1 ]
机构
[1] Univ Windsor, Dept Elect & Comp Engn, Windsor, ON N9B 3P4, Canada
关键词
D O I
10.1155/2014/529392
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Circuit reliability has become a growing concern in today's nanoelectronics, which motivates strong research interest over the years in reliability analysis and reliability-oriented circuit design. While quite a few approaches for circuit reliability analysis have been reported, there is a lack of comparative studies on their pros and cons in terms of both accuracy and efficiency. This paper provides an overview of some typical methods for reliability analysis with focus on gate-level circuits, large or small, with or without reconvergent fanouts. It is intended to help the readers gain an insight into the reliability issues, and their complexity as well as optional solutions. Understanding the reliability analysis is also a first step towards advanced circuit designs for improved reliability in the future research.
引用
收藏
页数:12
相关论文
共 50 条
  • [41] AC TDDB Analysis for Circuit-Level Gate Oxide Wearout Reliability Assessment
    Kopley, T. E.
    O'Brien, K.
    Chang, W. -C.
    [J]. 2016 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP (IIRW), 2016, : 73 - 76
  • [42] An Accurate Gate-level Stress Estimation for NBTI
    Han, Sangwoo
    Lee, Junho
    Kim, Byung-Su
    Kim, Juho
    [J]. JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2013, 13 (02) : 139 - 144
  • [43] Improving Gate-Level Simulation of Quantum Circuits
    Viamontes, George F.
    Markov, Igor L.
    Hayes, John P.
    [J]. QUANTUM INFORMATION PROCESSING, 2003, 2 (05) : 347 - 380
  • [44] Identification of Hardware Trojan in Gate-Level Netlist
    Mondal, Anindan
    Ghosh, Archisman
    Karmakar, Shubrojyoti
    Mahalat, Mahabub Hasan
    Roy, Suchismita
    Sen, Bibhash
    [J]. JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2024, 33 (09)
  • [45] RTL power optimization with gate-level accuracy
    Wang, Q
    Roy, S
    [J]. ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2003, : 39 - 45
  • [46] Exploiting behavioral information in gate-level ATPG
    Chiusano, S
    Corno, F
    Prinetto, P
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1999, 14 (1-2): : 141 - 148
  • [47] A BACKTRACING-ORIENTED PROCEDURE FOR THE ANALYSIS OF COMBINATIONAL GATE-LEVEL DESIGNS
    SILBERMAN, GM
    SPILLINGER, IY
    [J]. INTEGRATION-THE VLSI JOURNAL, 1994, 17 (03) : 271 - 286
  • [48] New approach in gate-level glitch modelling
    Rabe, D
    Nebel, W
    [J]. EURO-DAC '96 - EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL '96 AND EXHIBITION, PROCEEDINGS, 1996, : 66 - 71
  • [49] Temporal Parallel Gate-level Timing Simulation
    Kim, Dusung
    Ciesielski, Maciej
    Shim, Kyuho
    Yang, Seiyang
    [J]. HLDVT: 2008 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS, 2008, : 111 - +
  • [50] A Gate-Level Information Leakage Detection Framework of Sequential Circuit Using Z3
    Zhang, Qizhi
    Liu, Liang
    Yuan, Yidong
    Zhang, Zhe
    He, Jiaji
    Gao, Ya
    Li, Yao
    Guo, Xiaolong
    Zhao, Yiqiang
    [J]. ELECTRONICS, 2022, 11 (24)