共 50 条
- [21] Fast sequential circuit test generation using high-level and gate-level techniques [J]. DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS, 1998, : 570 - 576
- [24] AN UPPER-BOUND ALGORITHM FOR GATE-LEVEL DELAY ANALYSIS [J]. 1989 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS: PROCEEDINGS OF TECHNICAL PAPERS, 1989, : 232 - 236
- [25] 2022 CAD contest problem a: learning arithmetic operations from gate-level circuit [J]. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2022,
- [26] A unified compact model of the gate oxide reliability for complete circuit level analysis [J]. 2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 549 - +
- [27] Gate and circuit level analysis of n-type SRAM reliability failures [J]. MICROELECTRONICS AND RELIABILITY, 1997, 37 (10-11): : 1541 - 1544
- [29] A simplified gate-level fault model for crosstalk effects analysis [J]. 17TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2002, : 31 - 39
- [30] Gate-level simulation of quantum circuits [J]. ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, : 295 - 301