Gate and circuit level analysis of n-type SRAM reliability failures

被引：1
|
作者：
Symonds, K
Wilson, J
Lindo, P
Bahrami, M
机构：
[1] Digital Semiconductor, Hudson, MA 01749
来源：
MICROELECTRONICS AND RELIABILITY | 1997年 / 37卷 / 10-11期
关键词：
D O I：
10.1016/S0026-2714(97)00104-2
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Gate and circuit level analysis of n-type SRAM failures from experimental time dependent dielectric breakdown (TDDB) testing is presented. Advanced techniques used to successfully isolate and image gate level failure modes include thermally assisted optical emission, parallel polishing, selective polysilicon removal and ultra high resolution (UHR) backscatter electron microscopy. A circuit level failure model founded on confirmed defects is presented which predicts the failure mode distribution. Joule heating is shown to be the primary factor in accelerating defects from formation to catastrophic failure. (C) 1997 Elsevier Science Ltd.
引用
收藏
页码：1541 / 1544
页数：4
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