共 50 条
- [1] Exploiting Behavioral Information in Gate-Level ATPG [J]. Journal of Electronic Testing, 1999, 14 : 141 - 148
- [2] Improving gate-level ATPG by traversing concurrent EFSMs [J]. 24TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2006, : 172 - +
- [3] Improving ATPG gate-level fault coverage by using test vectors generated from behavioral HDL descriptions [J]. IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP, 2006, : 314 - +
- [4] Guided Gate-level ATPG for Sequential Circuits using a High-level Test Generation Approach [J]. 2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, : 420 - 425
- [7] Modular test generation and concurrent transparency-based test translation using gate-level ATPG [J]. PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2000, : 75 - 78
- [8] GATE-LEVEL INFORMATION-FLOW TRACKING FOR SECURE ARCHITECTURES [J]. IEEE MICRO, 2010, 30 (01) : 92 - 100
- [10] Static Gate-Level Information Flow for Hardware Information Security with Bounded Model Checking [J]. 2024 IEEE 42ND VLSI TEST SYMPOSIUM, VTS 2024, 2024,