共 50 条
- [41] Security Order of Gate-Level Masking Schemes [J]. 2023 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST, HOST, 2023, : 57 - 67
- [42] Scalable gate-level models for power and timing analysis [J]. 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 2938 - +
- [43] Using conjugate symmetries to enhance gate-level simulations [J]. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS, 2006, : 636 - 641
- [44] Optimal Design on Asynchronous System with Gate-level Pipelining [J]. PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2015,
- [46] Induction-based gate-level verification of multipliers [J]. ICCAD 2001: IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2001, : 190 - 193
- [47] Gate-Level Characterization: Foundations and Hardware Security Applications [J]. PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 222 - 227
- [48] Hardware IP Protection Through Gate-level Obfuscation [J]. 2015 14TH INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN AND COMPUTER GRAPHICS (CAD/GRAPHICS), 2015, : 186 - 193
- [49] Machine learning approach to gate-level evolvable hardware [J]. EVOLVABLE SYSTEMS: FROM BIOLOGY TO HARDWARE, 1997, 1259 : 327 - 343
- [50] Evolutionary design of gate-level polymorphic digital circuits [J]. APPLICATIONS OF EVOLUTIONARY COMPUTING, PROCEEDINGS, 2005, 3449 : 185 - 194