Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

An efficient architecture for a low jitter all digital phase locked loop (ADPLL) suitable for high speed system-on-chip (SoC) applications is presented in this article. The ADPLL is designed using standard cells and described by hardware description language. The ADPLL implemented in a 90-nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that the PLL has a cycle to cycle jitter of 164 ps at 100 MHz. Because the digitally controlled oscillator can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for SoC applications.