A Novel Time-to-Digital Converter Based on Low-Jitter Phase-Locked Loop

This paper presents a novel multi-levels time-to-digital converter (TDC) suitable for array architecture for the photon time-of-flight (TOF) measurement. A simple method was applied to solve the initial phase time mismatch caused by random occurrence of the TOF start signal. A low-jitter phase-locked loop (PLL) is adopted to provide excellent clocks to the TDC. The proposed PLL-TDC has a good differential nonlinearity (DNL) (+/- 0.4 LSB) and integral nonlinearity (INL) (+/- 0.5 LSB) due to the low-jitter clock and elimination of initial phase time mismatch. The circuit of the low-jitter PLL was implemented in TSMC 0.35 mu m standard complementary metal oxide semiconductor (CMOS) process with 3.3V supply voltage. The measured result of the low-jitter PLL and the simulated result of the TDC show the proposed 14-bit TDC can realize 1.0ns time resolution and 16 mu s maximum range with 125MHz centre frequency. Under this given frequency, the time interval error (TIE) jitter is 7.8 ps((rms)).