Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

被引：6
|
作者：
Moorthi, S. [1 ]
Meganathan, D. [2 ]
Janarthanan, D. [2 ]
Kumar, P. Praveen [2 ]
Perinbam, J. Raja Paul [3 ]
机构：
[1] Natl Inst Technol, Dept Elect & Elect Engn, Tiruchirappalli 5, Tamil Nadu, India
[2] Anna Univ, Dept Elect Engn, Madras 600044, Tamil Nadu, India
[3] Anna Univ, Coll Engn, Dept Elect & Commun Engn, Madras 600025, Tamil Nadu, India
来源：
INTERNATIONAL JOURNAL OF ELECTRONICS | 2009年 / 96卷 / 11期
关键词：
all digital phase locked loop (ADPLL); system-on-chip (SoC); phase locked loop (PLL); very high speed integrated circuit (VHSIC); hardware description language (VHDL); digitally controlled oscillator (DCO); phase frequency detector (PFD); voltage controlled oscillator (VCO);
D O I：
10.1080/00207210903017255
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An efficient architecture for a low jitter all digital phase locked loop (ADPLL) suitable for high speed system-on-chip (SoC) applications is presented in this article. The ADPLL is designed using standard cells and described by hardware description language. The ADPLL implemented in a 90-nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that the PLL has a cycle to cycle jitter of 164 ps at 100 MHz. Because the digitally controlled oscillator can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for SoC applications.
引用
收藏
页码：1183 / 1189
页数：7
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