Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits

被引：5

作者：

Wang, Ran ^{[1
]}

Chakrabarty, Krishnendu ^{[2
]}

机构：

[1] Duke Univ, Durham, NC 27708 USA

[2] Duke Univ, Engn, Dept Elect & Comp Engn, Durham, NC 27708 USA

来源：

IEEE DESIGN & TEST | 2017年 / 34卷 / 05期

关键词：

12;

D O I：

10.1109/MDAT.2017.2705077

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Editor's note: 2.5-D integrated circuit (IC) is a cost-efficient alternative to through-silicon-via (TSV)-based 3-D IC. In this paper, the authors give a comprehensive summary of the testing challenges of 2.5-D ICs and their existing solutions. They then present a test architecture using e-fuses for prebond interposer testing and a method to reduce power-supply noise during the testing. - Yiran Chen, Duke University. © 2013 IEEE.

引用

页码：72 / 79

页数：8

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