Power Delivery Network Benchmarking for Interposer and Bridge-Chip-Based 2.5-D Integration

In this letter, a power delivery network (PDN) modeling framework for emerging heterogeneous 2.5-D integration platforms is presented. The framework is validated using IBM power grid benchmarks, and maximum relative errors of less than 7.29% and 0.67% for IR-drop and transient noise are shown, respectively. Next, the framework is used to evaluate interposer and bridge-chip-based 2.5-D integration platforms. The simulation results show that an interposer with dense power/ground grids and microbumps can suppress power supply noise (PSN) by a small margin. In bridge-chip-based 2.5-D integration, under the assumption that the bridge-chips underneath the active dice block direct access to package power/ground planes, some PDN considerations are highlighted and evaluated. Using multiple bridge-chips and smaller overlap areas between the bridge-chips and the active dice, the worst case PSN in bridge-chip-based 2.5-D integration is minimally impacted.