A feasibility study on 100Gbps-per-channel die-to-die signal transmission on silicon interposer-based 2.5-D LSI with a passive digital equalizer

This paper proposes a passive equalizer that works as a digital filter compensating a large ISI (inter-symbol interference) of 100 Gbps or faster signal on high-loss signal lines on silicon interposers. The equalizer, which discretizes input signal through multiple signal reflection, is implemented on a silicon interposer, without need for circuit area and power supply on LSI (large-scale integration) die. In addition to the passive equalizer, a small amplitude, low impedance driver and a non-terminated receiver are employed for minimizing power consumption at the same time maximizing the signal amplitude at the receiver. A signal integrity simulation based on those design techniques has confirmed that 100 Gbps, NRZ (non return -to-zero) signal transmission is possible over 1/2-inch signal line on silicon interposer, as long as I/O parasitic load is sufficiently small. This result suggests the possibility of bandwidth expansion of the silicon interposer-based 2.5-D LSIs by decade times in the near future.