Fault diagnosis in scan-based BIST

被引：24
|
作者：
Rajski, J [1 ]
Tyszer, J [1 ]
机构：
[1] Mentor Graph Corp, Wilsonville, OR 97070 USA
来源：
ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY | 1997年
关键词：
D O I：
10.1109/TEST.1997.639704
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The paper presents a new fault diagnosis technique for scan-based BIST designs. It can be used for non-adaptive identification of the scan cells that are driven by erroneous signals, irrespective of the error multiplicity. The proposed scheme employs a simple scan cell selection hardware which in conjunction with a conventional signature analysis allows flexible trade-offs between the test application time and the diagnostic resolution.
引用
收藏
页码：894 / 902
页数：9
相关论文
共 50 条
  • [21] On acceleration of lest points selection for scan-based BIST
    Nakao, M
    Hatayama, K
    Higashi, I
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1998, E81D (07): : 668 - 674
  • [22] A ROMless LFSR reseeding scheme for scan-based BIST
    Kalligeros, E
    Kavousianos, X
    Nikolos, D
    PROCEEDINGS OF THE 11TH ASIAN TEST SYMPOSIUM (ATS 02), 2002, : 206 - 211
  • [23] Improving test effectiveness of scan-based BIST by scan chain partitioning
    Xiang, D
    Chen, MJ
    Sun, JG
    Fujiwara, H
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24 (06) : 916 - 927
  • [24] Scan-based delay fault tests for diagnosis of transition faults
    Pomeranz, Irith
    Reddy, Sudhakar M.
    21ST IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2006, : 419 - +
  • [25] Improving test quality of scan-based BIST by scan chain partitioning
    Xiang, D
    Chen, MJ
    Sun, JG
    Fujiwara, H
    ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2003, : 12 - 17
  • [26] A gated clock scheme for low power scan-based BIST
    Bonhomme, Y
    Girard, P
    Guiller, L
    Landrault, C
    Pravossoudovitch, S
    SEVENTH IEEE INTERNATIONAL ON-LINE TESTING WORKSHOP, PROCEEDINGS, 2001, : 87 - 89
  • [27] A hybrid algorithm for test point selection for scan-based BIST
    Tsai, HC
    Cheng, KT
    Lin, CJ
    Bhawmik, S
    DESIGN AUTOMATION CONFERENCE - PROCEEDINGS 1997, 1997, : 478 - 483
  • [28] Accelerated test points selection method for scan-based BIST
    Nakao, M
    Hatayama, K
    Higashi, I
    SIXTH ASIAN TEST SYMPOSIUM (ATS'97), PROCEEDINGS, 1997, : 359 - 364
  • [29] Efficient test-point selection for scan-based BIST
    Tsai, HC
    Cheng, KTT
    Lin, CJM
    Bhawmik, S
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1998, 6 (04) : 667 - 676
  • [30] Effectiveness of scan-based delay fault tests in diagnosis of transition faults
    Pomeranz, I.
    Reddy, S. M.
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2007, 1 (05): : 537 - 545
12345