Design-for-Testability Techniques for Arithmetic Circuits

In this paper, a novel test technique is proposed to achieve C-testable DFT designs for arithmetic circuits. Base on famous iterative-logic-array (ILA) test scheme, basic bijective cells (one-to-one mapped I/O function) for adder, subtractor, adder-subtractor and multiplier are proposed. In particular, these basic cells are always bijective for any word-length n. Thus the bijective cells can be easily connected together for various arithmetic circuits such as accumulator, multiplier and FIR (Finite Impulse Response) filter, and these arithmetic circuits can be regarded as C-testable ILAs. The proposed solutions can be reused or cascaded with similar structure circuits. Besides, all the proposed arithmetic DFT designs can be cascaded and tested together for saving lots of test pins and BIST (Build-In Self Test) area.