Design-for-Testability Techniques for Motion Estimation Computing Arrays

被引：0

作者：

Dong, Mao-Yang ^{[1
]}

Yang, Sheu-Hen ^{[1
]}

Lu, Shyue-Kung ^{[1
]}

机构：

[1] Fu Jen Catholic Univ, Dep Elect Engn, Taipei, Taiwan

来源：

2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2: VOL 1: COMMUNICATION THEORY AND SYSTEM | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a testable 2-D motion estimation (TME) design at the bit level (TMEbit) based on the C-testability conditions are proposed. In order to meet the testability conditions, the bit-level cell functions are made bijective. Our C-testability conditions guarantee about 100% fault coverage for single cell fault model with a constant number of test patterns. The number of test patterns is 128. To verify the proposed technique, an experimental chip is implemented with TSMC 0.18 mu m technology. According to experimental results, the gate count of the design is about 159 K and the design can operate at the frequency up to 100 MHz. The hardware overhead used to make it C-testable is about 7%.

引用

页码：1326 / 1329

页数：4

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