Fast 32-bit digital multiplier

This paper presents a high-speed VLSI implementation structure for multiplier. Four n-bit numbers are generated using even and odd positions of the two n-bit numbers. Then they are multiplied pairwise. Parallel addition algorithm is used to add tip partial products. Three k-bit numbers at each level are converted to two (k + 1)-bit numbers at the nest level using a 3-to-2 adding technique. Carry propagation is left to the last stage of multiplier where a fast carry-look-ahead adder is used to add the final two 2(n - 1)-bit numbers. The supply voltage (V-dd) is 3.3 upsilon which can be lowered to 8.5 upsilon. The multiplier are in 0.8 mu technology. HSPICE simulation shows a total delay of 3.25 ns for 32-bit multiplier.