A 32-bit Energy Efficient Exact Dadda Multiplier

In this paper, a 32-bit exact Dadda Multiplier is realized using 4:2 compressor. A Dadda Multiplier is similar to Wallace Multiplier. Both of the multipliers are used to reduce the partial products but Dadda Multiplier is faster than other multipliers and require less gates than Wallace Multiplier and a low power consumption. The compressors used has it's own accuracy level in both the exact and approximate mode with variable delay and less power consumption. Synopsys Design Compiler using SCL 180nm CMOS technology was used to evaluate the efficiency of the compressors in 32-bit Dadda Multiplier and compared with other 4, 8 and 16-bit Dadda multipliers. The results depicts around 48% decrease in power consumption with an area of 18955.74 mu m(2).