Comparison of a 32-Bit Vedic Multiplier With A Conventional Binary Multiplier

被引：0

作者：

Bisoyi, Abhyarthana ^{[1
]}

Baral, Mitu ^{[1
]}

Senapati, Manoja Kumar ^{[1
]}

机构：

[1] Natl Inst Sci & Technol, Dept Elect & Commun, Berhampur, Orissa, India

来源：

2014 INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES (ICACCCT) | 2014年

关键词：

Vedic mathematics; FPGA; binary multipliers; Xilinx; ISE;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Binary multipliers and addresses are used in the design and development of Arithmetic Logic Unit (ALU), Digital Signal Processing (DSP) Processors, Multiply and Accumulate (MAC). The objective of this paper is to implement digital multipliers based on the concept of Vedic mathematics. In order to develop a digital multiplier, Urdhva-tiryakbyham sutra of Vedic mathematics is used to implement vertical and cross wise operations. Since these are digital multipliers, they are implemented on FPGA board and are tested through the 8 LED (s) in FPGA (Nexys 3). A 32-bit Vedic multiplier has been simulated in Xilinx ISE 13.4 and has been compared with a 32-bit binary multiplier.

引用

页码：1757 / 1760

页数：4

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