32-bit constant (k) coefficient multiplier

被引：0

作者：

Al-Khalili, AJ ^{[1
]}

Zaman, NU ^{[1
]}

机构：

[1] Concordia Univ, Montreal, PQ, Canada

来源：

IEEE REGION 10 INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONIC TECHNOLOGY, VOLS 1 AND 2 | 2001年

关键词：

constant coefficient multiplier; FPGA; KCM algonthm; LUT (lookup table);

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper a 32-bit constant coefficient multiplier using KCM algorithm in Wallace tree format is presented. The proposed design, is compared with other constant coefficient multipliers and different general-purpose multipliers. For quantitative analysis the multipliers are synthesized in FPGA using Xilinx 4052xl-1 FPGA technology. The analysis presents a guideline to the ASIC designers for selection of an appropriate multiplier when delay, area, power or any combination of them is the primary objective.

引用

页码：306 / 308

页数：3

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