CLA based 32-Bit Signed Pipelined Multiplier

被引：0

作者：

Bokade, Smruti ^{[1
]}

Dakhole, Pravin ^{[1
]}

机构：

[1] YC Coll Engn, Dept Elect Engn, Nagpur 441110, Maharashtra, India

来源：

2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND SIGNAL PROCESSING (ICCSP), VOL. 1 | 2016年

关键词：

Modified Booth Encoder (MBE); Partial Product Rows (PPRs); Pipeline;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, Radix-4 Modified Booth Encoding (MBE) is used to generate partial product. The proposed 32-bit multiplier is based on pipelining. The main target is to reduce the delay of higher bits multiplier and speeding up the computation. The proposed design is implemented in Xilinx 14.2. The delay achieved is 2.826ns for computing 32x32 bit signed multiplication with maximum frequency of 353.832 MHz on the device 7vx330tffg1157-3.

引用

页码：849 / 852

页数：4

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