Fast 32-bit digital multiplier

被引：0

作者：

Raahemifar, K ^{[1
]}

Ahmadi, M ^{[1
]}

机构：

[1] Ryerson Polytech Univ, Dept Elect & Comp Engn, Toronto, ON M5B 2K3, Canada

来源：

ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ICECS.2001.957479

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents a high-speed VLSI implementation structure for multiplier, Four n-bit numbers are generated using even and odd positions of the two n-bit numbers. Then they are multiplied pairwise, Parallel addition algorithm is used to add up partial products. Three k-bit numbers at each level are converted to two (k + 1)-bit numbers at the next level using a 3-to-2 adding technique. Carry propagation is left. to the last stage of multiplier where a fast carry-look-ahead adder is used to add the final two 2(n - 1)-bit numbers. The supply voltage (V-dd) is 3,3 V which can be lowered to 2.5 v. The multiplier are in 0.8 mu technology. HSPICE simulation shows a total delay of 3.25 ns for 32-bit multiplier.

引用

页码：1413 / 1416

页数：4

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