Performance Analysis of Rectangular and Trapezoidal TG Bulk FinFETs for 20 nm Gate Length

被引：0
|
作者：
Gaurav, Ankit [1 ]
Gill, Sandeep S. [1 ]
Kaur, Navneet [1 ]
机构：
[1] Guru Nanak Dev Engn Coll, Dept Elect & Commun Engn, Ludhiana 141006, Punjab, India
来源：
2015 ANNUAL IEEE INDIA CONFERENCE (INDICON) | 2015年
关键词：
Rectangular; Trapezoidal; TG FinFETs; Bulk; Device; numerical simulation; DESIGN; MOSFETS;
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
FinFETs are the best alternatives or substitutes for the continuous downscaling of conventional MOSFETs. In this paper, the electrical performance of rectangular and trapezoidal TG bulk FinFETs for 20 nm gate length has been analyzed using 3D numerical device simulator. It was found that changing the fin shape from rectangular to trapezoidal leads to reduction in Short Channel Effects like leakage current, drain induced barrier lowering and subthreshold swing. The effects of change in equivalent fin width while moving from rectangular to trapezoidal fin shape on the device performance has also been studied.
引用
收藏
页数：5
相关论文
共 50 条
  • [21] 20nm gate bulk-FinFET SONOS flash
    Hwang, JR
    Lee, TL
    Ma, HC
    Lee, TC
    Chung, TH
    Chang, CY
    Liu, SD
    Perng, BC
    Hsu, JW
    Lee, MY
    Ting, CY
    Huang, CC
    Wang, JH
    Shieh, JH
    Yang, FL
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 161 - 164
  • [22] Analog/RF Performance of Thin (∼10 nm) HfO2 Ferroelectric FDSOI NCFET at 20 nm Gate Length
    Mehrotra, Shruti
    Qureshi, Shafi
    2018 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2018,
  • [23] Random-work-function-induced characteristic fluctuation in 16-nm-gate bulk and SOI FinFETs
    Li, Yiming
    Chen, Chieh-Yang
    Chen, Yu-Yu
    INTERNATIONAL JOURNAL OF NANOTECHNOLOGY, 2014, 11 (12) : 1029 - 1038
  • [24] High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond
    Liu, Q.
    Vinet, M.
    Gimbert, J.
    Loubet, N.
    Wacquez, R.
    Grenouillet, L.
    Le Tiec, Y.
    Khakifirooz, A.
    Nagumo, T.
    Cheng, K.
    Kothari, H.
    Chanemougame, D.
    Chafik, F.
    Guillaumet, S.
    Kuss, J.
    Allibert, F.
    Tsutsui, G.
    Li, J.
    Morin, P.
    Mehta, S.
    Johnson, R.
    Edge, L. F.
    Ponoth, S.
    Levin, T.
    Kanakasabapathy, S.
    Haran, B.
    Bu, H.
    Bataillon, J. -L.
    Weber, O.
    Faynot, O.
    Josse, E.
    Haond, M.
    Kleemeier, W.
    Khare, M.
    Skotnicki, T.
    Luning, S.
    Doris, B.
    Celik, M.
    Sampson, R.
    2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2013,
  • [25] Reliability investigation upon 30nm gate length ultra-high aspect ratio FinFETs
    Liao, WS
    Chen, SS
    Chiung, S
    Shiau, WT
    2005 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 43RD ANNUAL, 2005, : 541 - 544
  • [26] A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies
    Rahhal, Lama
    Bajolet, Aurelie
    Manceau, Jean-Philippe
    Rosa, Julien
    Ricq, Stephane
    Lassere, Sebastien
    Ghibaudo, Gerard
    SOLID-STATE ELECTRONICS, 2015, 108 : 53 - 60
  • [27] Effect of Gate Length Scaling on Various Performance Parameters in DG-FinFETs: a Simulation Study
    Vaid, Rakesh
    Chandel, Meenakshi
    JOURNAL OF NANO- AND ELECTRONIC PHYSICS, 2012, 4 (03)
  • [28] High Temperature Performance of Flexible SOI FinFETs with Sub-20 nm Fins
    Diab, A.
    Sevilla, G. A. Torres
    Ghoneim, M. T.
    Hussain, M. M.
    2014 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2014,
  • [29] Self-aligned Metallic Source and Drain Fin-on-Insulator FinFETs with Excellent Short Channel Effects Immunity down to 20 nm Gate Length
    Zhang, Qingzhu
    Li, Junjie
    Tu, Hailing
    Yi, Huaxiang
    Yan, Jiang
    Meng, Lingkuan
    Yao, Jiaxin
    Wang, Guilei
    Cao, Zhijun
    Li, Yudong
    Zhang, Zhaohao
    Wu, Zhenhua
    Wei, Feng
    Zhao, Hongbin
    Gao, Jiangfeng
    He, Xiaobin
    Jiang, Qifeng
    Xiong, Wenjuan
    Xiang, Jinjuan
    Zhou, Zhangyu
    Lu, Yihong
    Xu, Gaobo
    Luo, Kun
    Pan, Yu
    Xu, Renren
    Gu, Jie
    Hou, Chaozhao
    Li, Junfeng
    Wang, Wenwu
    2018 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2018,
  • [30] Density Gradient Quantum Corrections based Performance Optimization of Triangular TG Bulk FinFETs using ANN and GA
    Gaurav, Ankit
    Gill, Sandeep S.
    Kaur, Navneet
    Rattan, Munish
    2016 20TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT), 2016,
12345