共 50 条
- [1] Analysis of Influence of Temperature on 20nm Triangular Bulk FinFET 2016 IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2016, : 985 - 987
- [2] A NOVEL BULK-FINFET WITH DUAL-MATERIAL GATE 2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,
- [3] An opposite side floating gate FLASH memory scalable to 20nm length 2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2002, : 71 - 72
- [5] Mismatch trends in 20nm Gate-last bulk CMOS technology 2014 15TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (ULIS), 2014, : 133 - 136
- [6] Investigation of short channel effects in Bulk MOSFET and SOI FinFET at 20nm node technology 2015 ANNUAL IEEE INDIA CONFERENCE (INDICON), 2015,
- [8] Damascene gate FinFET SONOS memory implemented on bulk silicon wafer IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 893 - 896
- [9] A study of sub-40nm FinFET BE-SONOS NAND flash 2008 JOINT NON-VOLATILE SEMICONDUCTOR MEMORY WORKSHOP AND INTERNATIONAL CONFERENCE ON MEMORY TECHNOLOGY AND DESIGN, PROCEEDINGS, 2008, : 115 - +
- [10] Random dopant fluctuations impact reduction in 7 nm bulk-FinFET by substrate engineering INTERNATIONAL JOURNAL OF MATERIALS & PRODUCT TECHNOLOGY, 2019, 59 (04): : 339 - 346