Effect of Gate Length Scaling on Various Performance Parameters in DG-FinFETs: a Simulation Study

This paper presents a simulation study on the gate length scaling of a double gate (DG) FinFET. To achieve channel lengths smaller than 20 nm, innovative device architectures will be necessary to continue the benefits previously acquired through scaling. In order to obtain desirable control of short channel effects (SCEs), the thickness or the horizontal width of a fin in a FinFET should be less than two-third of its gate length and the semiconductor fin should be thin enough in the channel region to ensure forming fully depleted device. The effect of decreasing gate length (Lg) is to deplete more of the region under the inversion layer, which can be easily visualized if the source and drain are imagined to approach one another. If the channel length L is made too small relative to the depletion regions around the source and drain, the SCEs associated with charge sharing and punch through can become intolerable. Thus, to make L small, the depletion region widths should be made small. This can be done by increasing the substrate doping concentration and decreasing the reverse bias. Drain induced barrier lowering (DIBL) increases as gate length is reduced, even at zero applied drain bias, because the source and drain form pn junction with the body, and have associated built-in depletion layers associated with them that become significant partners in charge balance at short channel lengths, even with no reverse bias applied to increase depletion width. The subthreshold slope increases as the device becomes shorter. In fact, when the device becomes very short, the gate no longer controls the drain current and the device cannot be turned off. This is caused by punch through effect. The subthreshold swing (SS) changes with the drain voltage.