An on-chip learning neural network

被引：6
|
作者：
Bo, GM [1 ]
Caviglia, DD [1 ]
Valle, M [1 ]
机构：
[1] Univ Genoa, Dept Biophys & Elect Engn, I-16145 Genoa, Italy
来源：
IJCNN 2000: PROCEEDINGS OF THE IEEE-INNS-ENNS INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOL IV | 2000年
关键词：
D O I：
10.1109/IJCNN.2000.860751
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In this paper we present and discuss the major results of out research activity aimed to the analog VLSI implementation of on-chip learning neural networks. In particular we present the SLANP (Self Learning Neural Processor) chip results. The SLANP architecture implements an on-chip learning Multi Layer Perceptron network. The learning algorithm is based on the Back Propagation but it exhibits increased capabilities due to the local learning rate management. A prototype chip has been designed and fabricated in a CMOS 0.7 mu m minimum channel length technology. The experimental results confirm the functionality of the chip and the soundness of the approach. The SLANP performance compare favorable with those reported in literature.
引用
收藏
页码：66 / 71
页数：6
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