An on-chip learning neural network

被引：6
|
作者：
Bo, GM [1 ]
Caviglia, DD [1 ]
Valle, M [1 ]
机构：
[1] Univ Genoa, Dept Biophys & Elect Engn, I-16145 Genoa, Italy
来源：
IJCNN 2000: PROCEEDINGS OF THE IEEE-INNS-ENNS INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOL IV | 2000年
关键词：
D O I：
10.1109/IJCNN.2000.860751
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In this paper we present and discuss the major results of out research activity aimed to the analog VLSI implementation of on-chip learning neural networks. In particular we present the SLANP (Self Learning Neural Processor) chip results. The SLANP architecture implements an on-chip learning Multi Layer Perceptron network. The learning algorithm is based on the Back Propagation but it exhibits increased capabilities due to the local learning rate management. A prototype chip has been designed and fabricated in a CMOS 0.7 mu m minimum channel length technology. The experimental results confirm the functionality of the chip and the soundness of the approach. The SLANP performance compare favorable with those reported in literature.
引用
收藏
页码：66 / 71
页数：6
相关论文
共 50 条
  • [31] Realization of the CMOS pulsewidth-modulation (PWM) neural network with on-chip learning
    Bor, JC
    Wu, AY
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1998, 45 (01): : 96 - 107
  • [32] Neural Network based On-Chip Thermal Simulator
    Kumar, Pratyush
    Atienza, David
    2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 1599 - 1602
  • [33] Local cluster neural network on-chip training
    Zhang, Liang
    Sitte, Joaquin
    2006 IEEE INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORK PROCEEDINGS, VOLS 1-10, 2006, : 29 - +
  • [34] The CMOS design of robust neural chip with the on-chip learning capability
    Wu, CY
    Liu, RY
    Jou, IC
    ShyhJYE, FJ
    ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 3, 1996, : 426 - 429
  • [35] On-chip learning in pulsed silicon neural networks
    Lehmann, T
    Woodburn, R
    Murray, AF
    ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 693 - 696
  • [36] On-chip learning for a scalable hybrid neural architecture
    Alhalabi, BA
    Bayoumi, MA
    ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 677 - 680
  • [37] Mixed analogue-digital artificial-neural-network architecture with on-chip learning
    Schmid, A
    Leblebici, Y
    Mlynek, D
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1999, 146 (06): : 345 - 349
  • [38] A new mixed-signal feed-forward neural network with on-chip learning
    Mirhassani, M
    Ahmadi, M
    Miller, WC
    2004 IEEE INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1-4, PROCEEDINGS, 2004, : 1729 - 1734
  • [39] Securing On-Chip Learning: Navigating Vulnerabilities and Potential Safeguards in Spiking Neural Network Architectures
    Nazari, Najmeh
    Gubbi, Kevin Immanuel
    Latibari, Banafsheh Saber
    Chowdhury, Muhtasim Alam
    Fang, Chongzhou
    Sasan, Avesta
    Rafatirad, Setareh
    Homayoun, Houman
    Salehi, Soheil
    2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024, 2024,
  • [40] AN ALL-ANALOG EXPANDABLE NEURAL-NETWORK LSI WITH ON-CHIP BACKPROPAGATION LEARNING
    MORIE, T
    AMEMIYA, Y
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (09) : 1086 - 1093
12345