Hardware implementation of an on-chip BP learning neural network with programmable neuron characteristics and learning rate adaptation

被引：0
|
作者：
Lu, C [1 ]
Shi, BX [1 ]
Chen, L [1 ]
机构：
[1] Tsing Hua Univ, Inst Microelect, Beijing 100084, Peoples R China
来源：
IJCNN'01: INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1-4, PROCEEDINGS | 2001年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
An analog on-chip BP(Back-Propagation) learning neural network with programmable neuron characteristics and learning rate adaptation is designed and fabricated with 1.2-mum CMOS, double-poly, double-metal technology. A novel neuron circuit with programmable parameters is proposed. It generates not only the sigmoid function but also its derivative. Learning rate adaptation circuit is also presented to accelerate the convergence speed. The experiment of non-linear partition is done and the result verifies the function of this on-chip BP learning neural network.
引用
收藏
页码：212 / 215
页数：4
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