An on-chip learning neural network

In this paper we present and discuss the major results of out research activity aimed to the analog VLSI implementation of on-chip learning neural networks. In particular we present the SLANP (Self Learning Neural Processor) chip results. The SLANP architecture implements an on-chip learning Multi Layer Perceptron network. The learning algorithm is based on the Back Propagation but it exhibits increased capabilities due to the local learning rate management. A prototype chip has been designed and fabricated in a CMOS 0.7 mu m minimum channel length technology. The experimental results confirm the functionality of the chip and the soundness of the approach. The SLANP performance compare favorable with those reported in literature.