共 50 条
- [2] Hardware implementation of an on-chip BP learning neural network with programmable neuron characteristics and learning rate adaptation [J]. IJCNN'01: INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1-4, PROCEEDINGS, 2001, : 212 - 215
- [3] Circuit design of on-chip BP learning neural network with programmable neuron characteristics [J]. Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 2000, 21 (12): : 1164 - 1169
- [5] A general-purpose neural network with on-chip BP learning [J]. 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, PROCEEDINGS, 2002, : 520 - 523
- [6] An on-chip learning neural network [J]. IJCNN 2000: PROCEEDINGS OF THE IEEE-INNS-ENNS INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOL IV, 2000, : 66 - 71
- [8] Frequency-based multilayer neural network with on-chip learning and enhanced neuron characterisitcs [J]. IEEE TRANSACTIONS ON NEURAL NETWORKS, 1999, 10 (03): : 545 - 553
- [9] On-Chip Learning with a 15-neuron Digital Oscillatory Neural Network Implemented on ZYNQ Processor [J]. PROCEEDINGS OF INTERNATIONAL CONFERENCE ON NEUROMORPHIC SYSTEMS 2022, ICONS 2022, 2022,
- [10] An Analog Probabilistic Spiking Neural Network with On-Chip Learning [J]. NEURAL INFORMATION PROCESSING (ICONIP 2017), PT VI, 2017, 10639 : 777 - 785