CMOS design of a low power and high precision four-quadrant analog multiplier

被引：28

作者：

Beyraghi, Naser ^{[1
]}

Khoei, Abdollah ^{[1
]}

机构：

[1] Urmia Univ, Microelect Res Lab, Orumiyeh 57159, Iran

来源：

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2015年 / 69卷 / 01期

关键词：

CMOS analog multiplier; Four quadrant; Squarer circuit; Current mode; CURRENT-MODE; LOW-VOLTAGE; CIRCUITS;

D O I：

10.1016/j.aeue.2014.10.015

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a novel current-mode Four-quadrant analog multiplier is proposed. The newly designed current squarer circuits and one current mirror which all operate in low supply voltage (2 V) are the basic building blocks in realization of the mathematical equations. The multiplier circuit is designed by using 0.35 mu m standard CMOS technology and to validate the circuit performance, the proposed multiplier has been simulated in HSPICE simulator. The simulation results demonstrate a linearity error of 0.17%, a THD of 0.16% in 1 MHz, a -3 dB bandwidth of 485 MHz and a maximum power consumption of 0.232 mW while the static power consumption is 0.111 mW. (C) 2014 Elsevier GmbH. All rights reserved.

引用

页码：400 / 407

页数：8

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