A design of four-quadrant analog multiplier

被引：0

作者：

Dejhan, K ^{[1
]}

Prommee, P ^{[1
]}

Tiamvorratat, W ^{[1
]}

Mitatha, S ^{[1
]}

Chaisayun, I ^{[1
]}

机构：

[1] King Mongkuts Inst Technol, Fac Engn, Bangkok 10520, Thailand

来源：

IEEE INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES 2004 (ISCIT 2004), PROCEEDINGS, VOLS 1 AND 2: SMART INFO-MEDIA SYSTEMS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper proposes a new four quadrants analog multiplier which consists of a multiplier cell, a mixed signal circuit and three signal subtraction circuits. Its advantages are : this design has single ended inputs, the geometry of all transistors are equal, and its output can be the product of two signal voltage, or the product of a signal current and a signal voltage. Simulation results are demonstrated by PSpice to confirm the operation of the circuit.

引用

页码：29 / 32

页数：4

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