Investigation of Electrically Gate-All-Around Hexagonal Nanowire FET (HexFET) Architecture for 5 nm Node Logic and SRAM Applications

被引：0

作者：

Smith, Jeffery A. ^{[1
]}

Ni, Kai ^{[1
]}

Ghosh, Ram Krishna ^{[1
]}

Xu, Jeff ^{[2
]}

Badaroglu, Mustafa ^{[2
]}

Chidambaram, P. R. Chidi ^{[2
]}

Datta, Suman ^{[1
]}

机构：

[1] Univ Notre Dame, Notre Dame, IN 46556 USA

[2] Qualcomm Technol Inc, San Diego, CA USA

来源：

2017 47TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC) | 2017年

关键词：

5 nm Node; FinFET; Gate-All-Around Nanowire; Electrically Gate-All-Around Hexagonal Nanowire;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work investigates, in detail, the electrically gate-all-around (eGAA) Hexagonal NW FET (HexFET) which combines the high current drive of FinFETs with the excellent electrostatic robustness of conventional Gate-All-Around Nanowire (GAA NW) FETs. We evaluate HexFET as a potential successor to FinFET for 5nm node logic and SRAM applications using first principles atomistic-based modeling, calibrated 3D numerical device simulations, and circuit-level benchmarking. From this, we conclude that the eGAA HexFET architecture offers superior performance to both FinFET and GAA NW FET for 5nm node applications.

引用

页码：188 / 191

页数：4

共 50 条

[1] Tellurium Nanowire Gate-All-Around MOSFETs for Sub-5 nm Applications
Yin, Yiheng
Zhang, Zhaofu
Zhong, Hongxia
Shao, Chen
Wan, Xuhao
Zhang, Can
Robertson, John
Guo, Yuzheng
[J]. ACS APPLIED MATERIALS & INTERFACES, 2021, 13 (02) : 3387 - 3396
[2] Random Dopant Fluctuation in Gate-All-Around Nanowire FET
Tan, Cher Ming
Chen, Xiangchen
[J]. 2014 IEEE INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC), 2014,
[3] Modeling and analysis of gate-all-around silicon nanowire FET
Chen, Xiangchen
Tan, Cher Ming
[J]. MICROELECTRONICS RELIABILITY, 2014, 54 (6-7) : 1103 - 1108
[4] Metal Grain Granularity Study on a Gate-All-Around Nanowire FET
Nagy, Daniel
Indalecio, Guillermo
Garcia-Loureiro, Antonio J.
Elmessary, Muhammad A.
Kalna, Karol
Seoane, Natalia
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (12) : 5263 - 5269
[5] On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node
Wong, Hei
Kakushima, Kuniyuki
[J]. NANOMATERIALS, 2022, 12 (10)
[6] Gate-All-Around GaN Nanowire FET as a Potential Transistor at 5 nm Technology for Low-Power Low-Voltage Applications
Thakur, Rajiv Ranjan
Chaturvedi, Nidhi
[J]. NANO, 2021, 16 (08)
[7] Investigation of process variation in vertically stacked gate-all-around nanowire transistor and SRAM circuit
Sun, Yabin
Li, Xianglong
Zhuo, Yue
Liu, Yun
Wang, Teng
Li, Xiaojin
Shi, Yanling
Xu, Jun
Liu, Ziyu
[J]. SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2021, 36 (05)
[8] A Junctionless Gate-All-Around Silicon Nanowire FET of High Linearity and Its Potential Applications
Wang, Tao
Lou, Liang
Lee, Chengkuo
[J]. IEEE ELECTRON DEVICE LETTERS, 2013, 34 (04) : 478 - 480
[9] Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond
Bangsaruntip, S.
Balakrishnan, K.
Cheng, S. -L.
Chang, J.
Brink, M.
Lauer, I.
Bruce, R. L.
Engelmann, S. U.
Pyzyna, A.
Cohen, G. M.
Gignac, L. M.
Breslin, C. M.
Newbury, J. S.
Klaus, D. P.
Majumdar, A.
Sleight, J. W.
Guillorn, M. A.
[J]. 2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2013,
[10] Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET
Espineira, G.
Nagy, D.
Indalecio, G.
Garcia-Loureiro, A. J.
Kalna, K.
Seoane, N.
[J]. IEEE ELECTRON DEVICE LETTERS, 2019, 40 (04) : 510 - 513

← 1 2 3 4 5 →