Metrology needs for through-silicon via fabrication

被引：21

作者：

Vartanian, Victor ^{[1
]}

Allen, Richard A. ^{[2
]}

Smith, Larry ^{[1
]}

Hummler, Klaus ^{[1
]}

Olson, Steve ^{[1
,3
]}

Sapp, Brian ^{[1
]}

机构：

[1] SEMATECH, Ctr 3D, Albany, NY 12203 USA

[2] NIST, Semicond & Dimens Metrol Div, Gaithersburg, MD 20899 USA

[3] SUNY Albany, Coll Nanosci & Engn, Albany, NY 12203 USA

来源：

JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS | 2014年 / 13卷 / 01期

关键词：

interconnects; interferometry; metrology; optical inspection; semiconductors; x-rays;

D O I：

10.1117/1.JMM.13.1.011206

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper focuses on the metrology needs and challenges of through-silicon via (TSV) fabrication, consisting of TSV etch, liner, barrier, and seed (L/B/S) depositions, copper plating, and copper chemical mechanical planarization. These TSVs, with typical dimensions within a factor of two or so of approximate to 5 mu m x 50 mu m (diameter x depth), present an innovative set of metrology challenges because of the high aspect ratio and large feature sizes. The metallization deposition process includes thin layers of L/B/S metal; metrology for these layers determines whether there is complete coverage of the sidewalls. Metrology for the fill step includes verifying that the TSVs are deposited without voids and that the extent of stress on the surrounding silicon does not exceed acceptable limits. (C) 2014 Society of Photo-Optical Instrumentation Engineers (SPIE)

引用

页数：9

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