Voltage Clamping Requirements for ESD Protection of Inputs in 90nm CMOS Technology

被引：0
|
作者：
Lee, Jeffrey [1 ]
Rosenbaum, Elyse [1 ]
机构：
[1] Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA
来源：
ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS - 2008 | 2008年
关键词：
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
ESD reliability of MOS gate dielectrics and of input circuitry is investigated for a 90nm CMOS technology. Performance degradation is observed at voltages lower than the breakdown voltage. It is found that the input transistor gate dielectric breakdown voltage depends strongly on the source-body voltage and, consequently, on the input circuit design.
引用
收藏
页码：50 / 58
页数：9
相关论文
共 50 条
  • [1] ESD Protection Circuit for 8.5Gbps I/Os in 90nm CMOS Technology
    Sarbishaei, H.
    Sachdev, M.
    [J]. PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2009, : 697 - 700
  • [2] Voltage acceleration NBTI study for a 90nm CMOS technology
    Wen, SJ
    Hinh, L
    Puchner, H
    [J]. 2003 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP - FINAL REPORT, 2003, : 147 - 148
  • [3] 90nm generation RF CMOS technology
    Stamper, Anthony
    Bolam, Ronald
    Coolbaugh, Douglas
    Chanda, Kaushik
    Collins, David
    Dunn, James
    He, Zhong-Xiang
    Erturk, Mete
    Eshun, Ebenezer
    Lindgren, Peter
    McDevitt, Thomas
    Moon, Matthew
    Porth, Bruce
    Rathore, Hazara
    Onge, Stephen St.
    Snavely, Colleen
    Tiersch, Matthew
    Winslow, Arthur
    Zwonik, Robert
    [J]. ADVANCED METALLIZATION CONFERENCE 2007 (AMC 2007), 2008, 23 : 363 - 369
  • [4] Evaluation of SCR-based ESD protection devices in 90nm and 65nm CMOS technologies
    Di Sarro, James
    Chatty, Kiran
    Gauthier, Robert
    Rosenbaum, Elyse
    [J]. 2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL, 2007, : 348 - +
  • [5] Bootstrapped switch in low-voltage digital 90nm CMOS technology
    Lillebrekke, Christian
    Wulff, Carsten
    Ytterdal, Trond
    [J]. Norchip 2005, Proceedings, 2005, : 234 - 236
  • [6] NBTI reliability analysis for a 90nm CMOS technology
    Puchner, H
    Hinh, L
    [J]. ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2004, : 257 - 260
  • [7] Comparative analysis of comparators in 90nm CMOS Technology
    Khatak, Anil
    Kumar, Manoj
    Dhull, Sanjeev
    [J]. 2018 INTERNATIONAL CONFERENCE ON POWER ENERGY, ENVIRONMENT AND INTELLIGENT CONTROL (PEEIC), 2018, : 493 - 500
  • [8] An ultra low power ESD protected mixer in 90nm RF CMOS
    Salmeh, Roghoyeh
    [J]. IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS,, 2006, : 47 - 50
  • [9] A 60 GHz power amplifier in 90nm CMOS technology
    Heydari, Babak
    Bohsali, Mounir
    Adabi, Ehsan
    Niknejad, Ali M.
    [J]. PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2007, : 769 - 772
  • [10] Substrate isolation in 90nm RF-CMOS technology
    Barbier-Petot, Celine
    Bardy, Serge
    Biard, Christele
    Descamps, Philippe
    [J]. 35th European Microwave Conference, Vols 1-3, Conference Proceedings, 2005, : 89 - 92
12345