Voltage Clamping Requirements for ESD Protection of Inputs in 90nm CMOS Technology

被引：0
|
作者：
Lee, Jeffrey [1 ]
Rosenbaum, Elyse [1 ]
机构：
[1] Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA
来源：
ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS - 2008 | 2008年
关键词：
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
ESD reliability of MOS gate dielectrics and of input circuitry is investigated for a 90nm CMOS technology. Performance degradation is observed at voltages lower than the breakdown voltage. It is found that the input transistor gate dielectric breakdown voltage depends strongly on the source-body voltage and, consequently, on the input circuit design.
引用
收藏
页码：50 / 58
页数：9
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